Tradeoffs and Optimization in Analog CMOS Design

Condition: BRAND NEW ISBN: 9780470031360 Author(s): David Binkley Format: Hardcover Language: English Year: 2008 Edition: 1st Publisher: John Wiley & Sons Inc Pages: 632

Description: Analog CMOS integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choices of drain current, channel width, and channel length present for every MOS device in a circuit, these design choices afford significant opportunities for optimizing circuit performance. This book addresses tradeoffs and optimization of device and circuit performance for selections of the drain current, inversion coefficient, and channel length, where channel width is implicitly considered. The inversion coefficient is used as a technology independent measure of MOS inversion that permits design freely in weak, moderate, and strong inversion.A‚  This book details the significant performance tradeoffs available in analog CMOS design and guides the designer towards optimum design by describing: An interpretation of MOS modeling for the analog designer, motivated by the EKV MOS model, using tabulated hand expressions and figures that give performance and tradeoffs for the design choices of drain current, inversion coefficient, and channel length; performance includes effective gate-source bias and drain-source saturation voltages, transconductance efficiency, transconductance distortion, normalized drain-source conductance, capacitances, gain and bandwidth measures, thermal and flicker noise, mismatch, and gate and drain leakage currentMeasured data that validates the inclusion of important small-geometry effects like velocity saturation, vertical-field mobility reduction, drain-induced barrier lowering, and inversion-level increases in gate-referred, flicker noise voltageIn-depth treatment of moderate inversion, which